FIG. 1 is a schematic view for showing a conventional method for distributing interrupt tasks of a computer apparatus having a plurality of CPUs. Referring to FIG. 1, the computer apparatus 100 has five CPUs (as indicated by labels 102-110), a system bus 120 and a chipset 130. Each of the CPUs is electrically coupled to the chipset 130 via the system bus 120. In this present application, CPU is an interchangeable or equivalent term of processor or processor core. Furthermore, the computer apparatus 100 is suitable for coupling with a plurality of external hardware devices (such as external hardware devices as indicated by labels 152-160), and each of the external hardware devices is electrically coupled to the chipset 130.
Each of the CPUs transmits a task priority temporarily stored in a task priority register (TPR) therein to the chipset 130 according to a predetermined period, so as to notify the chipset 130 of the priority of the currently-performed task. Then the chipset 130 judges the current workloads of the CPUs according to the received task priorities. Therefore, when an external hardware device (which may be any one of the external hardware devices 152-160) sends out an interrupt request to the chipset 130, the chipset 130 can select a CPU of which the current workload is fewest (i.e., the CPU with the lowest task priority) from the CPUs to perform an interrupt task corresponding to the interrupt request.
However, since each of the CPUs will sends data to a corresponding cache thereof before performing a task and the CPU with the fewest current workload is altered along the time shift, this may cause a problem that the same data is sent to a cache of another CPU (of which the workload is fewest) again when the same external hardware device sends out the same interrupt request again. Therefore, the whole efficiency of the computer apparatus 100 is decreased.